The invention is directed to an improved approach for designing, analyzing, and manufacturing integrated circuits.
An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. Typically, geometric information about the placement of the nodes and components onto the chip is determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist. After an integrated circuit designer has created the physical design of the circuit, the integrated circuit designer then verifies and optimizes the design using a set of EDA testing and analysis tools.
Based upon the layout, photomasks are created for lithographic manufacturing of the electronic product. A photomask, or more simply a “mask,” provides the master image of one layer of a given integrated chip's physical geometries. A typical photolithography system projects UV light energy on to and through the mask in order to transmit the mask pattern in reduced size to the wafer surface, where it interacts with a photosensitive coating on the wafer. Other processes may also be performed during to manufacture an integrated circuit. For example, etching, electroplated copper deposition (ECD), and chemical mechanical polishing (CMP) may be used to form interconnects for the IC.
Significant variations may arise during the process of manufacturing the IC. These variations are commonly caused by side-effects of the processing used to manufacture the IC. For example, optical effects of using lithographic manufacturing process may cause variations to exist in the manufactured device from the originally intended feature dimensions and geometries of the layout. Variations in feature density, widths, and heights may also occur during the CMP, etching, and plating processes.
With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. In particular, the variations may lead to serious problems and flaws in the manufactured IC. This leads to serious risks of reduced manufacturing yield and increased failures for final products that incorporate the IC devices.
One particular area of concern is with regard to the management of leakage power in an IC product. As processing technology sizes shrink, the effects of process variations becomes quite significant towards its effects upon leakage power. Pattern-based effects within the manufactured IC devices may cause leakage currents in transistors to exceed allowable levels, which cause excessive amounts of leakage power to affect the performance and viability of the IC device.
One possible approach to managing leakage power with respect to process variations is for the IC manufacturing or fabrication facility to provide static maximum and minimum worst-case corner values that are used to analyze the circuit design. One problem with this approach is that the fabrication facility, commonly referred to as either the “fab” or “foundry”, is typically overly pessimistic with respect to the provided max and min values. Another problem is that as newer designs utilize smaller and smaller feature sizes, the range between the max and min values has become overly large relative to the designed feature sizes.
Therefore, it is clear that there is a need for an improved approach to perform leakage power analysis, characterization, and management. According to some embodiments of the invention, statistical leakage power analysis and characterization is employed as a method for estimating yield of a circuit in terms of leakage power. The present invention provides a method, system, and computer program product for performing statistical leakage power analysis/characterization with consideration of state correlation.
Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.